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CXA1884N
Low-voltage FM IF Amplifier
Description The CXA1884N is designed for FM communication devices. They incorporate a paging system, mixer, IF limiter, FM detector, operational amplifier, comparator, and others. Features * Low operating voltage 1.0 to 4.0V * Low power consumption 2mA at 1.5V * Built-in power source voltage monitor Applications IF Amplifier for Paging System Receiver Structure Bipolar silicon monolithic IC 20 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage Vcc 7 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 Recommended Operating Conditions Supply voltage Vcc 1.0 to 4.0
V C C
V
Block Diagram and Pin Configuration
VB OUT COMP IN A1 OUT
11 A1 QUAD DET. 10
SENSE
RF IN
20
19
18
17
16
15
14 ERR. AMP IF LIM.
13
12
MIXER
REG.
A2
OSC
1
2
3
4
5
6
7
8
MIX OUT
OSC2
IF IN
QD
A2 IN
9
GND
BSV
NRZ
LVA
OSC1
DET OUT
A1 IN
IF P1
IF P2
VCC
Note)
DET. : DETECTOR LIM. : LIMITER REG. : REGURATOR ERR. : ERROR CORRECTION
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97Z05A8Y
CXA1884N
Pin Description Pin No. Symbol Equivalent circuit Description
VCC
1
OSC1
1 2
2
OSC2
GND
Those pins are connected to the external parts of an oscillating circuit. The oscillator is an internally-biased Colpitts type with the collector, base, and emitter connections at Vcc, pins 1 and 2 respectively.
VCC 3
3
MIX OUT
Mixer output pin. Connect a 455kHz ceramic filter between this pin and the IF IN pin.
GND
4 5
VCC IF IN
VCC
Vcc pin. Input pin for the IF limiter amplifier.
5
6
IF P1
6
Connection pin of the bypass capacitor for the IF limiter amplifier. Connect a capacitor of about 0.047F between this pin and ground (or Vcc).
GND
VCC
7
IF P2
7
Connection pin of the bypass capacitor for the IF limiter amplifier. Connect a capacitor of about 0.047F between this pin and ground (or Vcc).
GND
VCC
8
QD
8
Connected to a quadrature detector phase shifter.
GND
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CXA1884N
Pin No.
Symbol
Equivalent circuit
Description
VCC
9
DET OUT
9
Recovered signal output.
GND
VCC
10
A1 IN
10
Input pin of inverting OP amplifier A1.
GND
VCC
11
A1 OUT
11
Output pin of OP amplifier A1.
GND
VCC
12
A2 IN
12
Input pin of OP amplifier A2.
GND
VCC
13
COMP IN
13
Input pin of the comparator. This pin is internally connected to the output of OP amplifier A2.
GND
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CXA1884N
Pin No.
Symbol
Equivalent circuit
Description
14
14
NRZ
GND
NRZ (Non Return Zero) output pin.
VCC
15
SENSE
15
Voltage control pin for external bias supply.
GND
VCC
16
VB OUT
16
Supplies bias voltage to external circuit transistors and others.
GND
17
17
BSV
GND
Reduces IC power consumption. Lowering pin voltage beiow 0.35V stops IC operation.
18
18
LVA
GND
Output pin for Low Voltage Alarm (LVA). The pin turns to high impedance when power voltage drops below 1.05V.
19
GND
VCC
Ground pin.
20
RF IN
20
Mixer input pin.
GND
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CXA1884N
Electrical Characteristics (VCC = 1.5V, Ta = 25C, fs = 21.7MHz, fMOD = 256Hz, fDIV = 2.3kHz, AMMOD = 30%) Item Symbol Condition Test circuit 1 Test circuit 1 VI = 0.3V Test circuit 3 VIN = 60dB Test circuit 3 Test circuit 2 Test ciTcuit 4 Test circuit 5 Test circuit 6 Test circuit 7 ISINK = 200A Test circuit 8 VB = 0.9V Test circuit 9 Test circuit 2 Test circuit 10 VPMH - VPML Test circuit 7 Test circuit 8 Test circuit 3 Min. 1.2 -- -- 25 -- 45 0.25 30 -- -- 0.1 0.95 85 1.00 35 -- -- 10 0.95 -- Typ. 2.0 -- 7 -- 30 60 -- 40 -- -- -- -- 100 1.05 50 -- -- -- -- -- Max. 2.6 20 -- -- 100 -- -- 50 5.0 0.4 -- -- 115 1.10 70 5.0 0.4 -- -- 0.35 Unit mA A dB dB nA dB Vp-p mV A V mA V mV V mV A V mVrms V V
Power consumption (during operation) ICC Power consumption (during battery saving) Input for -3dB Limiting AM rejection ratio OP amplifier input bias current OP amplifier open loop gain OP amplifier output voltage amplitude Comparator hysteresis width NRZ output leak current NRZ saturation voltage VB output current VB output voltage Sense voltage LVA threshold voltage LVA hysteresis width LVA output leak current LVA saturation voltage Recovered signal voltage BSV high level BSV low level NRZ: Non Return Zero ICCS VIN (LIM) AMRR IBIAS AV VO VTW ILNRZ VSATNRZ IOUT VBOUT VSEN VPML VPMTH ILLVA VSATLVA VDET VTHBSV VTLBSV
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CXA1884N
Electrical Characteristics Test Circuit
1 2 3 4 5 6 7 8 VCC 1.5V 9 10
20 19 18 17 16 15 14 13 12 11 VCC 1.5V VI 0.95V
1 2 3 4 5 6 7 8 9 10 RNF2 100k
20 19 18 17 16 15 14 13 12 11 RNF1 100k 7.5k 1k VI 0.95V
Test circuit 1
Test circuit 2
22p 15p CF1 455k CP1 0.047 CP2 0.047
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11 C IN 2 10 V IN 2 0.1Vp-p RNF2 10k VI 0.95V C IN 1 100p RL 50 V IN 1 21.7MHz VCC 1.5V
1 2 3 4 5 6 7 8 9 10 RNF2 10k
20 19 18 17 16 15 14 13 12 11 R IN 1 10k C IN 1 10 V IN 1 0.1Vp-p RNF1 10k VI 0.95V
4.7k VCC 1.5V
Vo
10
Test circuit 3
Test circuit 4
1 2 3 4 5 6 7 8 9 10 VCC 1.5V V IN2 0.1V
20 19 18 17 16 15 14 13 12 11 Vo VCC 1.5V V IN1 7V VI 0.95V
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11 V IN 0.2 to 0.3V VI 0.95V CP (C) RNF 10k
Test circuit 5
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Test circuit 6
RL 10k
CXA1884N
1 2 3 4 5 6 7 8 VCC 1.5V 9 10
20 19 18 17 16 15 14 13 12 11 VCC 1.5V VI 0.95V
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11 VI 0.3V IS1 200A RNF 10k VI 0.95V IS2 200A
Test circuit 7
VCC 1.5V
Test circuit 8
1 2 3 4 5 6 7 8 VCC 1.5V 9 10
20 19 18 17 16 15 14 13 12 11 VI 0.95V IS VS 0.15V 200A
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11 VI 0.95V CP (C)
VCC 1.5V
Test circuit 9
Test circuit 10
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CXA1884N
Test Method Input for -3dB Limiting VIN (LIM) Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 40dB Here, the value of VAC is specified as VAC1. Next, the signal level VL is changed to 19dB and VAC value is hence specified as VAC2. 20 log VAC1 VAC2 < 3dB
AM rejection ratio (AMRR) Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 40dB Here, the value of VAC is specified as VAC1. Next, AM is modified to: Modulation ratio: AMMOD = 30% Modulation frequency: fMOD = 256Hz and the VAC value is hence specified as VAC2. AMRR = 20 log VAC1 VAC2 > 25dB
Recovered signal voltage VDET Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 50dB Here, the value of the Pin 9 output voltage is expressed as VDET. OP amplifier output voltage amplitude VO Use test circuit 5. If output voltage V is expressed as V1 when VIN is 0.1V, and as V2 when VIN is 0.3V, it follows that: VO = V1 - V2 Comparator hysteresis width VTW Use test circuit 6. Vary VIN between 0.1 to 0.3V. Specify VIN voltage, as V1 when (C) voltage changes from low to high. Similarly, specify VIN voltage as V2, when (C) voltage changes from high to low. Therefore: VHY VTW = V1 - V2
LVA threshold voltage VPML and recovery voltage VPMH Use test circuit 10. Vary power voltage Vcc from 1.3 to 0.95V. Specify Vcc as VPML, when (C) voltage changes from low to high. Similarly, specify Vcc as VPMH, when (C) voltage changes from high to low. -8-
CXA1884N
Design Reference Values Item Mixer input resistance Mixer input capacity Mixer output resistance IF input resistance IF gain stability Detector output resistance OP amplifier max. input voltage OP amplifier min. input voltage Comparator max. input voltage Comparator min. input voltage OP amplifier off-set voltage Symbol RIN (MIX) CIN (MIX) ROUT (MIX) RIN (IF) GN (IF) ROUT (QD) VINMAX VINMIN VINMAXCOMP VINMINCOMP VOFS Ta = -20 to +60C Condition Min. 1.3 -- 1.44 1.44 -- 1.28 -- 0.05 -- 0.05 --
(Ta = 25C, Vcc = 1.4V) Typ. 1.6 4.0 1.8 1.8 6 1.6 -- -- -- -- -- Max. 1.9 -- 2.16 2.16 -- 2.0 0.39 -- 0.39 -- 3 Unit k pF k k dB k V V V V mV
Application Circuit
TO RF AMP TO 1ST MIX TO 2nd MIX
BATT.S DATA AUDIO LVA VCC 6.8k 27k 0.1 18 68k 56k R5 C4 13 12 R6 C3 R4 11
20
19
17
16
15
14
MIXER REG OSC
ERR
A2 A1 LIM DET
1 22p 20.945MHz
2
3
4
5
6
7 4.7k
8 4.7 (BP) or 1 1
9 R1
10
C2 R3 R2 C1
15p CFVM455
0.047 0.047
CDB455C3
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXA1884N
1) Supply This IC incorporates a regulation and is designed to operate steadily on a wide range of supply voltage from 1.0 to 4.0V. Decoupling on the wiring to the supply pin (Pin 4) should be done as close to the pin as possible. 2) Oscillation input Oscillation input method (a) Using Pins 1 and 2, input self-excited oscillation signals through the composition of a Colpitts type crystal oscillating circuit. (b) Input local oscillation signals to Pin 1 directly.
1
2
3 Ceramic filter
1
2
3 Ceramic filter
VCC From LOCAL SIG
(a) Fig. 1
(b)
3) Mixer This IC's mixer is of the double balance type. Pin 24 is the input pin. Input through a suitable alignment circuit. Input impedance is at 1.6k. The mixer output features a built-in 1.6k Ioad resistance at Pin 3. 4) IF filter The filter to be connected between this IC's mixer and the IF limiter should have the following specifications. I/O impedance: 1.6k 10% Band width: Use according to application
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CXA1884N
5) IF limiter The IF limiter of this IC features a gain of about 100dB. To this effect, the following points should be considered for the wiring connecting IF limiter input pin (Pin 5) and decoupling capacitor pins (Pins 6 and 7). (a) Wiring to mixer output (Pin 3) and IF limiter input (Pin 5) should be as short and as far apart as possible to avoid neutral interference. (b) Connect a decoupling capacitor to IF limiter IF P1 (Pin 6) and IF P2 (Pin 7). Here the decoupling capacitor should be positioned as close as possible to each pin and the wiring be as short as can be. (c) As IF limiter output shows at QD (Pin 8), keep the wiring connected to QD pin R, L, C and the ceramic discriminator as short as possible. Interference to the mixer output, IF limiter input and others must be kept to a minimum.
3
4
5
6
7
8
VCC
Wiring as short and as far apart as possible
As short as possible
Fig. 2
6) Detector The detector is of the quadrature type. To phase shift, either R, L, C resonance circuit or the ceramic discriminator is connected to Pin 8. The phase capacitor of the quadrature detector is built-in. FM (FSK) signals demodulated by this detector have their high frequency components dropped by the LPF formed inside from CRs, to be output at DET OUT (Pin 9). DET OUT output impedance is about 3k. For the CXA1884N ceramic discriminator, CDB 455 C3 (Murata Production) is recommended.
7 8 9 7 8 9
DET OUTPUT Coil VCC
4.7k
DET OUTPUT Ceramic discriminator CDB 455 C3
VCC
(a) Coil Fig. 3
(b) Ceramic discriminator
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CXA1884N
7) OP AMP, NRZ OUT This IC has 2 built-in operation amplifiers. One of these operation amplifiers is connected inside the IC to NRZ comparator.
14 13 12 11
0.2V
10
Fig. 4 Making use of these operation amplifiers an LPF or the sort is made up to eliminate noise during signal demodulation and input to the following NRZ comparator. NRZ comparator molds the waveform of input signals to output them as square waves. NRZ comparator output is an open collector. Accordingly as CPU is a CMOS, in case the supply voltage differs, by following the method indicated in Fig. 5 direct interfacing becomes possible.
VCC 1.5V
VCC
4 VCC for CMOS IC
14 NRZ OUT
CMOS IC
Fig. 5
8) VB SENSE, VB OUT This controls the base bias of the external transistor. Pin 16 VB OUT can be used as the previous amplifier 1st mixer bias. 9) LVA OUT When supply voltage turns low this pin turns to High (Open). Output is an open collector, and similarly as NRX OUT, can directly drive CMOS. This LVA setting voltage is at 1.05V 50mV with hysterisis versus supply voltage. Hysterisis width is at 50mV 10mV.
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CXA1884N
10) BSV By turning this pin to low, this IC's operation can be stopped. This pin can also be directly connected to CMOS. Consumption current with BSV is 20A (at 1.5V) and below.
17 BSV
Fig. 6
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CXA1884N
Mixer input signal vs. Output characteristics Input sensitivity
0 4. Length Butterworth Cascade MFB (G = 4) -10 1 33k 68k 9 -20 -30 -40 -50 -60 VCC = 1.5V, fMOD = 1kHz fDEV = 3kHz, fS = 21.7MHz fC = 1.5kHz, K = L67 (-3dB) 0.01 33k 470p A1 0.01 200mV 22k S+D+N
Output characteristics [dB]
12k
24k
2200p A2 200mV MIX 13 1000p 20 1.8H D+N S+D+N N
-120 -110 -100
-90
-80 -70 -60 -50 -40 Mixer input signal level [dBm]
-30
-20
-10
0
4th LP Butterworth cascade MFB constant using OP1 and OP2 inside CXA1884N
R2 C2 R4 A1 200mV C3 R6 R5 C4 A2 200mV 13
R1 9 C1
R3
fMOD fc (-3dB) A1 Gain A2 Gain R1 R2 R3 R4 R5 R6 C1 C2 C3 C4
256Hz 400Hz 1 4 47k 47k 22k 47k 180k 33k 0.012F 680pF 0.015F 1200pF
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CXA1884N
Supply voltage vs. Consumption current
4.0
Logical input level vs. Mixer conversion
20
ICC - Consumption current [mA]
Mixer conversion level [dB]
10 0 -10 A -20 B -30 -40 OSC IN Test the ratio between A and B. 20 f = 21.245MHz RF IN
3.0
2.0
1.0
2.0 3.0 VCC - Supply voltage [V]
4.0
0 -30 -20 -10 10 Logical input level [dBm]
Input frequency vs. Conversion gain
Conversion gain [dB]
10
0 LOCAL INPUT LEVEL = -10dBm
-10 1M 10M Input frequency [Hz] 100M
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CXA1884N
Package Outline
Unit: mm
20PIN SSOP (PLASTIC)
6.5 0.1 + 0.2 1.25 - 0.1 0.1 20 11 A
4.4 0.1
1
10 0.65 + 0.05 0.15 - 0.02
+ 0.1 0.22 - 0.05
0.13 M 0.1 0.1
0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L01 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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0.5 0.2
6.4 0.2

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